Recent measurements taken on NMOS and PMOS transistors implemented in sub-micron technologies have shown a great dependence of the threshold voltage values of the transistors on the channel length. Transistors realised in sub-micron technology provide a channel length below 1 μm. FIG. 1 shows a cross-section of a state of the art NMOS transistor in sub-micron technology on a bulk or wafer (6). The distance between n-doped-source (1) and -drain (2) under gate (3) in a p-doped-well 5 is referred to as the channel length (4). A small channel length variation which may be caused by tolerances in the fabrication process, can shift the threshold voltage value around 80 mV. FIG. 2 shows the qualitative evolution of the threshold voltage value versus the channel length L in logarithmic scale. When minimum length transistors with low threshold voltage values (Vt) are implemented (with Vt in the range from 0 mV to 400 mV), a small variation of the channel length has great impact on the threshold voltage value (see FIG. 2). This effect is referred to as Short Channel Effect. Therefore, the shift due to the uncertainty introduced in the channel length has a great impact in the performance of the device. Moreover, the impact on the performance of the circuits provided with these transistors is also highly affected in terms of static and dynamic terms. For digital circuits, static and dynamic power consumption increases and the performance in terms of speed is also affected. With regard to these problems, it is necessary to implement any kind of strategy capable to determine whether the length of minimum length devices (NMOS and PMOS transistors) is shifted and therefore causes a change in the threshold voltage value Vt.
Besides of the shifting in Vt due to variations in the channel length L, Vt can also change by reason of the doping dose used to implant the channel or a change in the thickness of the gate oxide. These two technology parameters, the doping dose and thickness of the oxide, will determine the status of the transistors. Three different status are allocated, “fast”, “nominal” and “slow” corresponding to small, nominal and high value of Vt, respectively. Short channel effects can appear in any one of these status of the technology.
Several strategies have been reported to establish a certain well potential bias in digital circuits when this bias is necessary. Well known strategies are based on delay lines and off current detection. Delay lines are formed by several transistors in series. Therefore, a change of the Vt value of the transistors changes the introduced delay. In dependence of the introduced delay the well potential bias is applied. The strategy based on delay lines can also be realised using critical path replicas. U.S. Pat. No. 6,091,283 describes a sub-threshold leakage tuning circuit which aims to compensate for process, activity and temperature-induced device threshold variations in a semiconductor circuit having a transistor, a potential of the gate wherein the transistor is held to a preset subthreshold potential and a channel current of the channel region is compared with a reference current to obtain a comparison result. A bias potential of a substrate is adjusted according to the comparison result to hold the subthreshold current at the reference current. The reference current is provided by a separate reference source. The device under test (DUT) is configured in a circuit in which the current is compared with said isolated reference current. The proposed method does only provide a solution for compensation for changes in device characteristics across process and temperature.
Another well known strategy is based on detection of the off current. However, some of these strategies require the use of band gap references to allow proper operation for a large range of temperatures. Moreover, none of these strategies allow to compare the performance of a DUT with the performance of a long channel device operating as a reference without requiring any additional temperature reference circuit.